The present invention relates to semiconductor packaging, and more particularly, to forming electrical connections in multi-die packages where the dies are disposed within different media.
Quality is a very important factor in the automated manufacturing of products, such as semiconductor packages. Faulty semiconductor packages having defects, particularly defects in wire bonds of the packages, are responsible for a significant number of customer returns. One cause of such defects is broken bond wires and/or broken wire bonds. Such defects can occur during, for example, quality assurance testing of the semiconductor packages, such as reliability stress testing. Obviously, a high incidence of failures is undesirable. Even less desirable is a situation whereby a given semiconductor package passes internal quality checks only to fail after being shipped to a customer.
There are several known issues with wire bond failures in semiconductor packages requiring die to die interconnections through wire bonding. Referring to FIG. 1, a first type of known failure is illustrated. A conventional semiconductor device 100 includes a first die 102 and a second die 104, both of which are disposed upon die pads of a lead frame 106. The first die 102 has stud bumps 108 that form termination points on the die 102 for bond wires 110a, 110b. A first bond wire 110a is connected directly to the lead frame 106 and a second bond wire 110b is connected to a lead finger or bond pad 112 of the lead frame 106.
Likewise, the second die 104 has first and second stud bumps 114 that form termination points for first and second bond wires 116a, 116b from the second die 104. The first bond wire 116a is also connected to the lead finger or bond pad 112, while the second bond wire 116b is connected directly to the lead frame 106. The bond wires 110b and 116a effect an electrical connection between the first and second dies 102, 104 by way of the lead finger or bond pad 112.
The second die 104 is encapsulated within a mould compound 118, such as a thermosetting resin typically used in a semiconductor mould encapsulation process. The first die 102 is encapsulated within an encapsulation gel 120, also typically used in semiconductor manufacturing processes. The encapsulation gel 120 is constrained between a package wall 122 and the mould compound 118. A boundary 124 is formed where the mould compound 118 meets with and constrains the encapsulation gel 120. A void 126 is provided for thermal expansion and movement of the encapsulation gel 120. A mould cap or lid 128 is provided to avoid any leakage or spillage of the encapsulation gel 120.
A significant problem with an arrangement such as that of FIG. 1 is that in the region marked 130 the bond wire 116a is exposed to thermal stresses caused by the transition from one encapsulation medium to the other. More specifically, the stresses may be caused due to the fact that each of the encapsulation media has a different coefficient of thermal expansion (CTE), meaning that in instances where the semiconductor device 100 is subjected to heating, each of the encapsulation media 118, 120 expands at a different rate. As will be appreciated, such CTE mismatches may have a detrimental effect on the bond wire 116a, and cause damage thereto, such as breakage in the region 130. In turn, this can lead to device failure, a highly undesirable situation for numerous reasons.
The semiconductor device 100 may be one that is used in, for example, a PDA or a smart phone. In such applications, the second die 104 is a microcontroller (MCU) and the first die 102 is a sensor such as a pressure cell or gravity cell used in many applications in PDAs/smart phones. It is necessary to provide the sensor within a gel 120 because, depending on the precise application and nature of the sensor, pressure on, or movement of, the sensor is necessary for its detecting function. It is generally not possible for these types of sensors to be encapsulated with the mould compound 118 as the mould compound 118 is typically cured or set. Use of encapsulation gel itself is not without its problems, as will now be discussed with reference to FIGS. 2 and 3.
FIG. 2 illustrates a semiconductor package 200 disposed within encapsulation gel 202. A bond wire 204 is formed in the package 200 from the die to either of a bond pad or a lead frame and a second bond wire 206 is formed for connection to another die (not shown in FIG. 2). Typically in such installations, it is necessary for the gel 202 to cover 70% or more of the height of the bond wire 206 as indicated by arrow 208. The control of coverage is determined by the configuration of the package/die and this causes difficulties in controlling the packaging process. If there is too much or too little of the gel 202, a stress mismatch is created that may leads to broken wires in this area.
Referring now to FIG. 3, a second type of known failure in a device having a die to die interconnection will now be discussed. A conventional semiconductor device 300 has first, second and third dies 302, 304, 306, all of which are disposed upon a lead frame 308. Die to die interconnections are formed between the first die 302 and the second die 304 and also between the second die 304 and the third die 306 with bond wires 310. The dies 302, 304, 306 and the bond wires 310 are encapsulated by encapsulation gel 314 filled in the mould to a level allowing an expansion void 316 between an upper surface of the encapsulation gel 314 and a mould lid 318.
Typically successful formation of such die to die interconnections presents challenges and is generally considered to be amongst the more complex of wire bonding techniques, requiring relatively delicate processes such as bond over pad or ball stitch on ball (BSOB) bonding. The formation of the wire bond connection on the second die requires great care otherwise the wiring traces at the second termination point on the die can be damaged. Additionally, arrangements typified by the example of FIG. 3 require large volumes of the gel 310. An undesirable side-effect of this is that it has been found that a larger volume of gel can lead to higher stresses on the bond wires 310 thereby leading to high failure rates of the bond wires 310, including breakages at regions 312. Furthermore, a CTE mismatch also arises between the bond wires 310 themselves and the gel 314 which, in turn, also causes further stresses on the wires 310.
Thus, it would be advantageous to be able to assemble a semiconductor device that is less susceptible to failures caused by encapsulation material CTE mismatches.